Method and apparatus for data sampling

ABSTRACT

A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a logic LSI in which input dataare sampled in synchronization with a clock signal.

BACKGROUND OF THE INVENTION

[0002] A conventional logic LSI includes a logic circuit, a register anda PLL (Phase Locked Loop) circuit. The register is connected to a clockinput terminal to an output terminal of the PLL circuit. The registerreceives input data and generates an output signal Q in synchronizationwith a clock signal generated in the PLL circuit to have a constantphase. In other words, the logic circuit samples the input data insynchronization with the constant clock signal.

[0003] According to the conventional logic LSI, if the input data isshifted in phase, the logic circuit could not sample the input dataproperly and mistakenly generates an unexpected output data.

OBJECTS OF THE INVENTION

[0004] Accordingly, an object of the present invention is to provide adata sampling circuit in which input data are sampled at appropriatetimings to provide reliability of data sampling even if the input dataare phase-shifted.

[0005] Another object of the present invention is to provide a method inwhich input data are sampled at appropriate timings to providereliability of data sampling even if the input data are phase-shifted.

[0006] Additional objects, advantages and novel features of the presentinvention will be set forth in part in the description that follows, andin part will become apparent to those skilled in the art uponexamination of the following or may be learned by practice of theinvention. The objects and advantages of the invention may be realizedand attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

[0007] According to a first aspect of the present invention, alevel-turning point of input data is detected; and a sampling clock isgenerated in response to the level-turning point of the input data. Theinput data are sampled in synchronization with the sampling clock. Theinput data can be sampled at an appropriate point or timing, because thesampling clock is generated in response to the level-turning point ofthe input data. A level-turning point means a point where the level of asignal changes to the opposite sate, for example, the point can becalled “signal rising point” or “signal falling point”. A sampling pointmeans a point where the input data are sampled.

[0008] Preferably, the sampling clock has a sampling point provided inthe middle of a normal cycle of the input data. The sampling clock maybe generated in response to the base clock having a frequency that iseight times greater than the normal frequency of the input data.

[0009] In an embodiment, a plurality of source clocks is generated tohave different phases shifted one by one, and one of the source clocksis selected as the sampling clock.

[0010] In another embodiment, an average phase signal representing theaverage of phase of plural source clocks, provided in the past, isgenerated. One from the average phase signal and currently generatedsampling clock is selected to provide a sampling clock to be actuallyused for sampling process. Preferably, a previous sampling clock andcurrently generated sampling clock are compared to detect a phasedifference between them; and the sampling operation is prohibited whenthe phase difference between the previous sampling clock and currentlygenerated sampling clock is larger than a predetermined threshold value.According to this embodiment, it is not necessary to generate a samplingclock for each cycle of the input data. As a result, power consumptionof the circuit can be reduced.

[0011] In another embodiment, the sampling clock has a firstlevel-turning point synchronizing with a level-turning point of theinput data and a second level-turning point provided right in the middleof a normal cycle of the input data. More precisely, a source clock,which is to be a source of the sampling clock, is generated. The sourceclock is compared with a predetermined reference signal, and the phaseof the source clock is controlled in response to a result of thecomparison. According to this embodiment, the sampling point can beprovided at the same timing from the level-turning point of the inputdata regardless the frequency of the base clock. For instance, thesampling point is provided after four cycles of base clock from thedetected level-turning point of the input data.

[0012] According to a second aspect of the present invention, a datasampling circuit includes an edge detecting circuit which detectslevel-turning points of input data; a sampling clock generating circuitwhich generates a sampling clock in response to the level-turning pointof the input data; and a logic circuit which samples the input data insynchronization with the sampling clock.

[0013] Preferably, according to an embodiment, a data sampling circuitincludes a PLL (Phase Locked Loop) circuit which generates a base clockhaving a frequency that is greater than a normal frequency of inputdata; an edge detecting circuit which detects level-turning points ofthe input data in response to the base clock; a source clock generatingcircuit which generates, in response to the base clock, a plurality ofsource clocks having different phases shifted by one cycle of the baseclock one by one; a clock selecting circuit which selects one from theplural source clocks as the sampling clock so that the sampling clockhas a first level-turning point synchronizing with a first level-turningpoint of the input data and a second level-turning point generated rightin the middle of the normal cycle of the input data; and a logic circuitsampling the input data in synchronization with the sampling clock.

[0014] Preferably according to another embodiment, a data samplingcircuit includes a PLL (Phase Locked Loop) circuit which generates abase clock having a frequency that is greater than a normal frequency ofinput data; an edge detecting circuit which detects level-turning pointsof the input data in response to the base clock; a source clockgenerating circuit which generates a source clock in response to thebase clock; a sampling clock generating circuit which generates asampling clock having a sampling point provided in the middle of anormal cycle of the input data; and a logic circuit sampling the inputdata in synchronization with the sampling clock. The sampling clockgenerating circuit includes a source clock generating circuit whichgenerates a source clock, which is to be a source of the sampling clock;and a frequency register which provides a reference signal. The sourceclock generating circuit compares the source clock with the referencesignal; and controls the phase of the source clock in response to aresult of the comparison.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1A is a block diagram showing a conventional logic LSI.

[0016]FIG. 1B is a timing chart showing the operation of theconventional logic LSI, shown in FIG. 1A.

[0017]FIG. 2 is a block diagram showing a logic LSI according to a firstpreferred embodiment of the present invention.

[0018]FIG. 3 is a block diagram showing an edge detecting circuit usedin the logic LSI, shown in FIG. 2.

[0019]FIG. 4 is a block diagram showing a source clock generatingcircuit used in the logic LSI, shown in FIG. 2.

[0020]FIG. 5 is a timing chart showing the operation of the logic LSI,shown in FIG. 2.

[0021]FIG. 6 is a block diagram showing a logic LSI according to asecond preferred embodiment of the present invention.

[0022]FIG. 7 is a block diagram showing a sampling-clock generatingcircuit used in the logic LSI, shown in FIG. 6.

[0023]FIG. 8 is a block diagram showing the detailed structure of aclock generating circuit used in the sampling-clock generating circuit,shown in FIG. 7.

[0024]FIG. 9 is a timing chart showing the operation of the logic LSI,shown in FIG. 6.

[0025]FIG. 10 is a block diagram showing a logic LSI according to athird preferred embodiment of the present invention.

DETAILED DISCLOSURE OF THE INVENTION

[0026] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which formapart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and scope of the presentinventions is defined only by the appended claims.

[0027] The invention is described in greater detail hereinafter relativeto a non-limitative embodiment and with reference to the attacheddrawings, wherein show:

[0028] For better understanding of the present invention, a conventionaltechnology is first described in conjunction with FIGS. 1A and 1B. FIG.1A is a block diagram showing a conventional logic LSI; and FIG. 1B is atiming chart showing the operation of the conventional logic LSI, shownin FIG. 1A. A conventional logic LSI 100 includes a logic circuit 101, aregister 102 and a PLL (Phase Locked Loop) circuit 103. The register 102is connected to a clock input terminal to an output terminal of the PLLcircuit 103. The register 102 receives input data RD and generates anoutput signal Q in synchronization with a clock signal generated in thePLL circuit 103 to have a constant phase. In other words, the logiccircuit 101 samples the input data RD in synchronization with theconstant clock signal CLK.

[0029] According to the conventional logic LSI 100, shown in FIG. 1A, ifthe input data RD is shifted in phase, the logic circuit 101 could notsample the input data RD properly and mistakenly generates an unexpectedoutput data Q0, as shown in FIG. 1B.

[0030] First Preferred Embodiment

[0031]FIG. 2 is a block diagram showing a logic LSI according to a firstpreferred embodiment of the present invention. A logic LSI 200 accordingto the first preferred embodiment includes a logic circuit (samplingcircuit) 201, a PLL circuit 202, an edge detecting circuit 203, asource-clock generating circuit 204 and a clock selecting circuit 205.Input data RD are supplied to the logic circuit 201 and edge detectingcircuit 203. The PLL circuit 202 is connected at an output terminal toinput terminals of the edge detecting circuit 203 and source-clockgenerating circuit 204. The PLL circuit 202 supplies a base clock CLK tothe edge detecting circuit 203 and source clock generating circuit 204.

[0032] The edge detecting circuit 203 is connected to an output terminalto an input terminal of the clock-selecting circuit 205. The edgedetecting circuit 203 supplies an ENB signal to the clock-selectingcircuit 205. The edge detecting circuit 203 detects level-turning pointsof the input data RD in synchronization with the base clock CLK andgenerates the ENB signal when a level-turning point of the input data RDis detected.

[0033] The source-clock generating circuit 204 is connected at an outputterminal to another input terminal of the clock selecting circuit 205.The source-clock generating circuit 204 supplies source clocks SCLKs tothe clock selecting circuit 205. The source-clock generating circuit 204generates source-clocks SCLK[0] to SCLK[7] in synchronization with thebase clock CLK supplied from the PLL circuit 202. The clock selectingcircuit 205 is connected at an output terminal to another input terminalof the logic circuit 201. The clock selecting circuit 205 supplies asampling clock RCLK to the logic circuit 201.

[0034] The clock selecting circuit 205 selects one clock from the eightsource-clocks SCLK[0] to SCLK[7], supplied from the source-clockgenerating circuit 204, in response to the ENB signal, supplied from theedge detecting circuit 203. The logic circuit 201 samples the input dataRD in synchronization with the sampling clock RCLK, supplied from theclock-selecting circuit 205.

[0035]FIG. 3 is a block diagram showing the edge detecting circuit 203,shown in FIG. 2. The edge detecting circuit 203 includes a register 206and an exclusive OR gate 207. The input data RD are supplied to an datainput terminal of the register 206 and to an input terminal of theexclusive OR gate 207. The register 206 is supplied at a clock inputterminal with the base clock CLK, supplied from the PLL circuit 202. Theregister 206 is connected at an output terminal Q to the other inputterminal of the exclusive OR gate 207. The exclusive OR gate 207 isconnected at an output terminal to the clock selecting circuit 205. Inthis embodiment, the base clock CLK is generated to have a frequencyeight times greater than a normal frequency of the input data RD. Thenormal frequency is in that the input data RD are supplied to the LSI ata proper timing according to the circuitry design.

[0036]FIG. 4 is a block diagram showing the source-clock generatingcircuit 204 used in the logic LSI 200, shown in FIG. 2. The source-clockgenerating circuit 204 includes a 3-bit counter and eight FF (Flip-Flop)circuits supplying source clocks SCLK[0] to SCLK[7], respectively.

[0037] Now the operation of the logic LSI 200, shown in FIG. 2 isdescribed in reference to a timing chart shown in FIG. 5. It is assumedthat the input data RD is undesirably phase-shifted, so that the signalRD is turned in level to high at t0, to low at t2 and is turned to highat t4. In the normal operation in which no phase-shift is made to theinput data RD, the input data RD would be turned to low at t3 and isturned to high at t6, as shown with a dashed line. When the input dataRD is turned in level to high “1” at t0, the signal ENB is turned to“1”. The signal ENB is turned to “0” at t1. The signal ENB keeps itshigh state for one cycle of the base clock CLK every time when the inputdata RD is level-turned.

[0038] As shown in FIG. 4, when output signal CNT of the 3-bit counteris 4, 5, 6 or 7, CNT[2] becomes “1”. When the output signal CNT of the3-bit counter is 0, 1, 2 or 3, CNT[2] becomes “0”. The source clockSCLK[0] has a phase one cycle delay to the CNT[2]. Since eight FFcircuits are serially connected, the source clocks SCLK[0] to SCLK[7]have different phases shifted one by one. The difference corresponds toone cycle of the base clock CLK.

[0039] It is prefer that the input data RD are sampled insynchronization with the sampling clock RCLK within a period of timebetween t0 and t2. In other words, such a sampling clock RCLK isrequired and generated. Accordingly, a clock that turns to high fourcycles later from t0 is selected as a sampling clock RCLK. It means thatthe sampling clock RCLK should be turned in level in a middle of thenormal cycle of the input data RD. Preferably, the sampling clock RCLKis turned in level right in the middle of the normal cycle of the inputdata RD. For sampling the input data within a period between t0 to t2,the source clock SCLK[4], which is turned in level at t0, is selected asa sampling clock RCLK. The clock SCLK[4] is used until another signalENB is generated at t2. In the same manner, the source clocks SCLK[3]and SCLK[4] are selected at t2 and t4, respectively, as the samplingclock RCLK.

[0040] As it can be understood, according to the first preferredembodiment, the sampling clock RCLK is generated in a middle of thenormal cycle of the input data RD; and therefore, the input data RD canbe sampled at an appropriate point or timing even if it is phase-shiftedto some extent. As a result, the chance of sampling error is reduced.

[0041] In this application, a level-turning point means a point wherethe level of a signal changes to the opposite sate, for example, thepoint can be called “signal rising point” or “signal falling point”. Asampling point means a point where the input data are sampled.

[0042] Second Preferred Embodiment

[0043]FIG. 6 is a block diagram showing a logic LSI according to asecond preferred embodiment of the present invention. A logic LSI 300according to the second preferred embodiment includes a logic circuit301, a PLL circuit 302, an edge detecting circuit 303 and asampling-clock generating circuit 304. Input data RD are supplied to thelogic circuit 301 and edge detecting circuit 303. The PLL circuit 302 isconnected at an output terminal to input terminals of the edge detectingcircuit 303 and sampling-clock generating circuit 304. The PLL circuit302 supplies a base clock CLK to the edge detecting circuit 303 andsampling-clock generating circuit 304.

[0044] The edge detecting circuit 303 is connected to an output terminalto an input terminal of the sampling-clock generating circuit 305 tosupply an ENB signal thereto. The edge detecting circuit 303 detectslevel-turning points of the input data RD in synchronization with thebase clock CLK and generates the ENB signal when a level-turning pointof the input data RD is detected. The sampling-clock generating circuit304 is connected at an output terminal to another input terminal of thelogic circuit 301.

[0045] The sampling-clock generating circuit 304 generates a samplingclock RCLK in response to the ENB signal, supplied from the edgedetecting circuit 303. The logic circuit 301 samples the input data RDin synchronization with the sampling clock RCLK, supplied from thesampling-clock generating circuit 304.

[0046] Since the PLL circuit 302 and edge detecting circuit 303 may bethe same as those for the first preferred embodiment, shown in FIGS. 2and 3, the same description is no repeated hear for the second preferredembodiment.

[0047]FIG. 7 is a block diagram showing the sampling-clock generatingcircuit 304 used in the logic LSI 300, shown in FIG. 6. Thesampling-clock generating circuit 304 includes a frequency register 312,a clock generating circuit 314 and a 6-bit register 316. The frequencyregister 312 is connected at an output terminal to an input terminal ofthe clock generating circuit 314.

[0048] The frequency register 312 provides a numeral signal FS inaccordance with software or the like. The signal FS is calculated by aformula of “x/2−1”, where “x” indicates eight in this embodiment becausethe frequency of the base clock CLK is eight times greater than thenormal frequency of the input data RD. Accordingly, in this embodiment,the frequency register 312 provides the signal FS indicating “3”. Thefrequency register 312 may be designed to store an uneven numberselected one from 1, 3, 5, . . . 29, 31. If the 6-bit register 316 isdesigned to store more bits, the frequency register 312 could have moreselection of numeral data stored therein. “x” can be up to 64 in thissystem, but must be even number.

[0049] The clock generating circuit 314 is connected at other two inputterminals to the output terminal of the edge detecting circuit 303,shown in FIG. 6, and an output terminal of the 6-bit register 316. Theclock generating circuit 314 is connected at an output terminal to aninput terminal of the 6-bit register 316. The clock generating circuit314 generates a clock signal CLKCI in accordance with the numeral signalFS, supplied from the frequency register 312, the signal ENB, suppliedfrom the edge detecting circuit 303, and with an output signal CLKC,supplied from the 6-bit register 316.

[0050] The 6-bit register 316 is connected at the output terminal to theinput terminal of the logic circuit 301, shown in FIG. 6. The signalCLKCI, supplied from the clock generating circuit 314, is set to one “1”when the signal ENB is one “1”. The signal CLKCI is incremented when thesignal ENB is zero “0”. Even if the signal ENB is zero “0”, CLKCI[4:0]is set to zero “0” when CLKC[4:0]=FS and CLKCI[5] is set to a numeralthat is the inverted value of CLKC[5]. The last bit CLKC[5] of CLKC,supplied from the 6-bit register 316 is picked up and used as a samplingclock RCLK.

[0051]FIG. 8 is a block diagram showing the detailed circuitry of theclock generating circuit 314, shown in FIG. 7. The clock generatingcircuit 314 includes an adder 320, a comparator 321, selectors 322 and323 and an inverter 324.

[0052] The comparator 321 is connected at an input terminal to theoutput terminal of the 6-bit register 316 and at an output terminal to acontrol terminal of the selector 322. The comparator is supplied withthe signal FS from the frequency register 312. The comparator 321compares the signals CLKC[4:0], corresponding to the last five bits ofCLKC, to the FS signal, and supplies signals one “1” and zero “0” whenthose compared signals CLKC[4:0] and FS are identical and not identical,respectively.

[0053] The adder 320 is connected at an input terminal to the outputterminal of the 6-bit register 316 and at an output terminal to an to aninput terminal of the selector 322. The adder 320 adds one “1” toCLKC[4:0]. The inverter 324 is connected at an output terminal to theother input terminal of the selector 322. The inverter 324 invertsCLKC[5], which is the first one bit of CLKC, and supplies the invertedsignal together with five-bit zero data “00000” to the selector 322.

[0054] The selector 322 is connected at an output terminal to an inputterminal of the selector 323. When a signal “1” is supplied from thecomparator 321 to the selector 322, the selector 322 selects thecombination of the output of the inverter 324 and five-bit zero data“00000”. When a signal “0” is supplied from the comparator 321 to theselector 322, the selector 322 selects the combination of the output(CLKC[4:0]+1) of the adder 320 and CLKC[5].

[0055] The selector 323 is supplied at a control terminal and the otherinput terminal with the ENB signal from the edge detecting circuit 303and six-bit one data “000001”, respectively. The selector 323 isconnected at an output terminal to the input terminal of the 6-bitregister 316. When the ENB is one “1”, the selector 323 selects thesignal “000001”. When the ENB is zero “0”, the selector 323 selects theoutput of the selector 322.

[0056] Next the operation of the clock generating circuit 314, shown inFIG. 8 is described in reference to a timing chart shown in FIG. 9.Until time tA, the signal ENB is zero and the signal CMP is zero, sothat CLKCI includes last five bits corresponding to the output of theadder 320 and the first one bit of CLKC[5], At time tA, signal FS(=2) isthe same as CLKC[4:0], the comparator 321 supplies a CMP indicating one“1”. Since the signal ENB is zero “0” and CMP is one “1”, CLKCI includeslast five bits corresponding to “00000” and the first one bit of zero“0”, which is the inverted value of CLKC[5].

[0057] At time t0, since the signal ENB is one “1” and CMP is zero “0”,CLKCI becomes “000001”. Since both the signals ENB and CMP keep zero “0”in a period of time between t1 to tB, CLKCI includes last five bitscorresponding to the output of the adder 320 and the first one bit ofCLKC[5]. At time tB, since CLKC[4:0] is the same as the signal FS(=3),the signal CMP becomes one “1”. In this case, CLKCI includes last fivebits of zero and the first one bit of one “1”, which is the invertedvalue of CLKC[5]. Since both the signals ENB and CMP keep zero untiltime tC, CLKCI includes last five bits corresponding to the output ofthe adder 320 and the first one bit of CLKC[5].

[0058] At time tC, since CLKC[4:0] is the same as the signal FS(=3), thesignal CMP becomes one “1”. Since the signal ENB is zero “0” and thesignal CMP is one “1”, CLKCI includes last five bits of zero and thefirst one bit of zero “0”, which is the inverted value of CLKC[5].Namely, CLKCI indicates zero “0”. In the same manner, CLKCI is generatedand is supplied to the 6-bit register 316 in synchronization with thebase clock CLK.

[0059] Now the operation of the logic LSI 300, shown in FIG. 6 isdescribed in reference again to the timing chart shown in FIG. 9. It isassumed that the input data RD is undesirably phase-shifted, so that thesignal RD is turned in level to high at t0, to low at t3 and is turnedto high at t5. In the normal operation in which no phase-shift is madeto the input data RD, the input data RD would be turned in level to lowat t2 and is turned to high at t6, as shown with a dashed line. It isalso assumed that the frequency of the base clock CLK is eight timesgreater than the normal frequency of the input data RD, so that thefrequency register 312 provides the signal FS indicating “3”.

[0060] When the input data RD is turned in level to high “1” at t0, thesignal ENB is turned to “1”. The signal ENB is turned to “0” at t1. Thesignal ENB is turned to high “1” for one cycle of the base clock CLKevery time when the input data RD is level-turned.

[0061] The CLKC is incremented continuously, and the CLK[4:0] is resetto zero “0” and CLKC[5] is reversed or inverted when CLK[4:0] becomesFS(=3) at t0. When the signal ENB turns to one “1” at t0, CLKCI[4:0] isset to one “1”. After that, CLKC[4:0] turns to one “1” at t1. CLKC[4:0]is a value indicated by 0^(th) to 4^(th) bits (last four bits) of asignal CLKC, and CLKC[5] is a value indicated by 5^(th) bit (first onebit) of the signal CLKC[5].

[0062] When CLKC[4:0] becomes FS(=3) at t2, CLKC[5] is reversed orinverted and CLKC[4:0] is turned to zero “0”. CLKC[4:0] is incrementedby one at t3. When the signal ENB becomes one “1” at t4 and t6,CLKC[4:0] is turned to one “1”. CLKC[5] is used as the sampling clockRCLK so that the sampling clock RCK is always level-turned after fourclock cycles of the base clock CLK, since the input data RD is firstturned in level (t0). In other words, the sampling clock RCLK has asampling point right in the middle of the normal cycle of the input dataRD,

[0063] As it can be understood, according to the second preferredembodiment, the sampling clock RCLK is generated right in the middle ofthe normal cycle of the input data RD; and therefore, the input data RDcan be sampled at an appropriate point or timing even if it isphase-shifted to some extent. As a result, the chance of sampling erroris reduced.

[0064] Further, according to this embodiment, the sampling point can beprovided at the same timing from the level-turning point of the inputdata RD regardless the frequency of the base clock CLK. For instance,the sampling point is provided after four cycles of base clock from thedetected level-turning point (t0) of the input data RD.

[0065] Third Preferred Embodiment

[0066]FIG. 10 is a block diagram showing a logic LSI according to athird preferred embodiment of the present invention. A logic LSI 400according to the third preferred embodiment includes a logic circuit401, a PLL circuit 402, an edge detecting circuit 403, a source-clockgenerating circuit 404, a clock selecting circuit 405 and a clock-phasestoring circuit 407. Input data RD are supplied to the logic circuit 401and edge detecting circuit 403. The PLL circuit 402 is connected at anoutput terminal to input terminals of the edge detecting circuit 403 andsource-clock generating circuit 404 to supply a base clock CLK thereto.

[0067] The edge detecting circuit 403 is connected to an output terminalto an input terminal of the clock-selecting circuit 405 to supply an ENBsignal thereto. The edge detecting circuit 403 detects level-turningpoints of the input data RD in synchronization with the base clock CLKand generates the ENB signal when a level-turning point of the inputdata RD is detected. The source-clock generating circuit 404 isconnected at an output terminal to another input terminal of the clockselecting circuit 405 to supply source clocks SCLKs thereto. Thesource-clock generating circuit 404 generates source-clocks SCLK[0] toSCLK[7] in synchronization with the base clock CLK supplied from the PLLcircuit 402. The clock selecting circuit 405 is connected at an outputterminal to another input terminal of the logic circuit 401 to supply asampling clock RCLK thereto.

[0068] The clock-phase storing circuit 407 is connected at an inputterminal to another output terminal of the clock selecting circuit 405and is connected at output terminals of input terminals of the clockselecting circuit 405 and logic circuit 401. The clock-phase storingcircuit 407 stores a plurality of selected clock numbers CLKS, suppliedfrom the clock selecting circuit 405; and calculate the average of thosenumbers to supply an average data signal CLKC to the clock selectingcircuit 405.

[0069] The clock selecting circuit 405 selects one clock from the eightsource-clocks SCLK[0] to SCLK[7], supplied from the source-clockgenerating circuit 404, in response to the ENB signal, supplied from theedge detecting circuit 403. After that the clock selecting circuit 405select one of the selected source clock and average data signal CLKC togenerate a sampling clock RCLK, to be supplied to the logic circuit 401.For example, the selected source clock is used as a sampling clock RCLKwhen a large amount of phase shift is made; and the average data signalCLKC is used as a sampling clock RCLK when the phase shift or phasedifference between the currently selected source clock SCLK and thepreviously selected clock is smaller than a predetermined level. If suchthe phase shift or phase difference is larger than a predeterminedreference value causing sampling errors, the clock-phase storing circuit407 supplies an interrupt signal INT to the logic circuit 401 so thatthe logic circuit 401 does not perform sampling process but gets in astandby or waiting mode.

[0070] In this embodiment, an average phase signal representing theaverage of phase of plural source clocks, provided in the past, isgenerated in the clock-phase storing circuit 407. One from the averagephase signal and currently generated sampling clock is selected toprovide a sampling clock RCLK to be actually used for sampling process.A previous sampling clock and currently generated sampling clock arecompared to detect a phase difference between them; and the samplingoperation is prohibited when the phase difference between the previoussampling clock and currently generated sampling clock is larger than apredetermined threshold value.

[0071] The edge detecting circuit 403 may be the same as the circuit203, shown in FIG. 3; and the source-clock generating circuit 404 may bethe same as the circuit 204, shown in FIG. 4. The same description forthose circuits is not repeated in this embodiment.

[0072] As it can be understood, according to the third preferredembodiment, the sampling clock RCLK is generated in the middle of thenormal cycle of the input data RD; and therefore, the input data RD canbe sampled at an appropriate point or timing even if it is phase-shiftedto some extent. As a result, the chance of sampling error is reduced.

[0073] Further according to this embodiment, it is not necessary togenerate a sampling clock for each cycle of the input data. As a result,power consumption of the circuit can be reduced.

[0074] The above-described PLL circuits 202, 302 and 402 can be arrangedoutside the logic LSI 400.

What is claimed is:
 1. A method for sampling input data, comprising thesteps of: detecting a level-turning point of the input data; generatinga sampling clock in response to the level-turning point of the inputdata; and sampling the input data in synchronization with the samplingclock.
 2. A method according to claim 1, wherein the sampling clock isgenerated to have a sampling point in the middle of a normal cycle ofthe input data.
 3. A method according to claim 1, further comprising thestep of: providing a base clock having a frequency that is greater thana normal frequency of the input data, wherein the sampling clock isgenerated in response to the base clock.
 4. A method according to claim1, wherein the level-turning point of the input data are detected inresponse to the base clock.
 5. A method according to claim 3, whereinthe base clock has a frequency that is eight times greater than thenormal frequency of the input data.
 6. A method according to claim 1,further comprising the steps of: generating a plurality of source clock;and selecting one of the source clocks as the sampling clock.
 7. Amethod according to claim 6, wherein the source clocks have differentphases shifted one by one.
 8. A method according to claim 7, wherein asource clock having a level-turning point synchronizing with thelevel-turning point of the input data is selected as the sampling clockso that the next level-turning point of the selected source clock isgenerated right in the middle of the normal cycle of the input data. 9.A method according to claim 6, further comprising the steps of:generating an average phase signal representing the average of phase ofplural source clocks, provided in the past; and selecting one from theaverage phase signal and currently generated sampling clock to provide asampling clock to be actually used for sampling process.
 10. A methodaccording to claim 9, further comprising the step of: comparing aprevious sampling clock and currently generated sampling clock to detecta phase difference between them; and prohibiting the sampling operationwhen the phase difference between the previous sampling clock andcurrently generated sampling clock is larger than a predeterminedthreshold value.
 11. A method for sampling input data, comprising thesteps of: providing a base clock having a frequency that is greater thana normal frequency of the input data; detecting a level-turning point ofthe input data in response to the base clock; generating responsive tothe base clock a plurality of source clocks having different phasesshifted by one cycle of the base clock one by one; selecting one fromthe plural source clocks as a sampling clock so that the sampling clockhas a first level-turning point synchronizing with the level-turningpoint of the input data and a second level-turning point generated rightin the middle of the normal cycle of the input data; and sampling theinput data in synchronization with the sampling clock.
 12. A methodaccording to claim 11, further comprising the steps of: generating anaverage phase signal representing the average of phases of plural sourceclocks, provided in the past; selecting one from the average phasesignal and currently generated sampling clock to provide a samplingclock to be actually used for sampling process; comparing a previoussampling clock and currently generated sampling clock to detect a phasedifference between them; and prohibiting the sampling operation when thephase difference between the previous sampling clock and currentlygenerated sampling clock is larger than a predetermined threshold value.13. A method according to claim 1, wherein the sampling clock has afirst level-turning point synchronizing with the level-turning point ofthe input data and a second level-turning point provided right in themiddle of a normal cycle of the input data.
 14. A method according toclaim 13, further comprising the steps of: generating a source clock,which is to be a source of the sampling clock; providing a referencesignal; comparing the source clock with the reference signal; andcontrolling the phase of the source clock in response to a result of thecomparison.
 15. A method for sampling input data, comprising the stepsof: providing a base clock having a frequency that is greater than anormal frequency of the input data; detecting a level-turning point ofthe input data in response to the base clock; generating a source clockin response to the base clock; providing a reference signal; comparingthe source clock with the reference signal; controlling the phase of thesource clock in response to a result of the comparison so as to generatea sampling clock having a first level-turning point synchronizing withthe level-turning point of the input data and a second level-turningpoint provided right in the middle of a normal cycle of the input data;and sampling the input data in synchronization with the sampling clock.16. A data sampling circuit, comprising: an edge detecting circuit whichdetects a level-turning point of input data; a sampling clock generatingcircuit which generates a sampling clock in response to thelevel-turning point of the input data; and a logic circuit which samplesthe input data in synchronization with the sampling clock.
 17. A datasampling circuit according to claim 16, wherein the sampling clock isgenerated to have a sampling point in the middle of a normal cycle ofthe input data.
 18. A data sampling circuit according to claim 16,further comprising: a PLL (Phase Locked Loop) circuit which generates abase clock having a frequency that is greater than a normal frequency ofthe input data, wherein the sampling clock is generated in response tothe base clock.
 19. A data sampling circuit according to claim 16,wherein the edge detecting circuit detects the level-turning point ofthe input data in response to the base clock.
 20. A data samplingcircuit according to claim 18, wherein the base clock has a frequencythat is eight times greater than the normal frequency of the input data.21. A data sampling circuit according to claim 16, wherein the samplingclock generating circuit comprises a source clock generating circuitwhich generates a plurality of source clocks; and a clock selectingcircuit which selects one of the source clocks as the sampling clock.22. A data sampling circuit according to claim 21, wherein the sourceclocks are generated to have different phases shifted one by one.
 23. Adata sampling circuit according to claim 22, wherein the clock selectingcircuit selects a source clock that has a level-turning pointsynchronizing with the level-turning point of the input data so that thenext level-turning point of the selected source clock is generated rightin the middle of the normal cycle of the input data.
 24. A data samplingcircuit according to claim 21, further comprising: a clock-phase storingcircuit which generates an average phase signal representing the averageof phases of plural source clocks, provided in the past; and selects onefrom the average phase signal and currently generated sampling clock toprovide a sampling clock to be actually used for sampling process.
 25. Adata sampling circuit according to claim 24, wherein the clock-phasestoring circuit compares a previous sampling clock to currentlygenerated sampling clock to detect a phase difference between them; andprohibits the sampling operation when the phase difference between theprevious sampling clock and currently generated sampling clock is largerthan a predetermined threshold value.
 26. A data sampling circuit,comprising: a PLL (Phase Locked Loop) circuit which generates a baseclock having a frequency that is greater than a normal frequency ofinput data; an edge detecting circuit which detects a level-turningpoint of the input data in response to the base clock; a source clockgenerating circuit which generates, in response to the base clock, aplurality of source clocks having different phases shifted by one cycleof the base clock one by one; a clock selecting circuit which selectsone from the plural source clocks as the sampling clock so that thesampling clock has a first level-turning point synchronizing with thelevel-turning point of the input data and a second level-turning pointgenerated right in the middle of the normal cycle of the input data; anda logic circuit sampling the input data in synchronization with thesampling clock.
 27. A data sampling circuit according to claim 26,further comprising: a clock-phase storing circuit which generates anaverage phase signal representing the average of phase of plural sourceclocks, provided in the past; selects one from the average phase signaland currently generated sampling clock to provide a sampling clock to beactually used for sampling process; compares a previous sampling clockand currently generated sampling clock to detect a phase differencebetween them; and prohibits the sampling operation when the phasedifference between the previous sampling clock and currently generatedsampling clock is larger than a predetermined threshold value.
 28. Adata sampling circuit according to claim 16, wherein the sampling clockhas a first level-turning point synchronizing with the level-turningpoint of the input data and a second level-turning point provided rightin the middle of a normal cycle of the input data.
 29. A data samplingcircuit according to claim 28, wherein the sampling clock generatingcircuit comprises a source clock generating circuit which generates asource clock, which is to be a source of the sampling clock; and afrequency register which provides a reference signal, wherein the sourceclock generating circuit compares the source clock with the referencesignal; and controls the phase of the source clock in response to aresult of the comparison.
 30. A data sampling circuit, comprising: a PLL(Phase Locked Loop) circuit which generates a base clock having afrequency that is greater than a normal frequency of input data; an edgedetecting circuit which detects a level-turning point of the input datain response to the base clock; a source clock generating circuit whichgenerates a source clock in response to the base clock; a sampling clockgenerating circuit which generates a sampling clock having a samplingpoint provided in the middle of a normal cycle of the input data; and alogic circuit sampling the input data in synchronization with thesampling clock, wherein the sampling clock generating circuit comprises:(1) a source clock generating circuit which generates a source clock,which is to be a source of the sampling clock; and (2) a frequencyregister which provides a reference signal, wherein the source clockgenerating circuit compares the source clock with the reference signal;and controls the phase of the source clock in response to a result ofthe comparison.